1. Field of the Invention
The present invention relates to a compensation circuit which compensates for variations in both temperature and supply voltage of an integrated circuit. More specifically, the present invention relates to a compensation circuit which ensures that predetermined currents are routed through a compensated circuit when the compensated circuit is operated with pre-defined ranges of temperature and supply voltage.
2. Discussion of Related Art
FIG. 1 is a schematic diagram of a CMOS inverter 100 which includes p-channel field effect transistor (FET) 101, n-channel FET 102, input terminal 103 and output terminal 104. P-channel FET 101 and n-channel FET 102 are connected in series between the V.sub.CC voltage supply terminal and the ground voltage supply terminal as illustrated. When the signal (IN) applied to input terminal 103 has a logic high value (i.e., V.sub.CC), n-channel FET 102 is turned on, and p-channel FET 101 is turned off. At this time, a current I.sub.N102 flows between output terminal 104 and the ground voltage supply terminal. When the IN signal applied to input terminal 103 has a logic low value (i.e., 0 volts), p-channel FET 101 is turned on, and n-channel FET 102 is turned off. At this time, a current I.sub.P101 flows between the V.sub.CC voltage supply terminal and output terminal 104.
Inverter 100 is typically fabricated on a semiconductor chip. On the chip, the temperature and V.sub.CC supply voltage can vary. For example, a V.sub.CC voltage supply having a specified voltage of 3.3 Volts may vary from a low of 2.8 Volts to a high of 3.8 Volts. As the temperature and V.sub.CC supply voltage vary, the intrinsic resistances and capacitances of FETs 101 and 102 will vary. The variations in resistance and capacitance, in turn, cause the currents I.sub.P101 and I.sub.N102 to vary. Moreover, the variations in resistance and capacitance undesirably result in variations in the speed of signal propagation through inverter 100 and/or variations in the gain of inverter 100. As a result, inverter 100 typically only meets the design specifications for a very narrow range of temperatures and V.sub.CC supply voltages. This is unacceptable in high performance circuits.
A first class of circuits has been provided to compensate for current variations that result from variations in temperature. A second class of circuits has been provided to compensate for current variations that result from variations in the V.sub.CC supply voltage. However, none of these circuits are capable of simultaneously compensating for current variations that result from both variations in temperature and variations in the V.sub.CC supply voltage.
It would therefore be desirable to have a circuit that compensates for current variations which result from both variations in temperature and variations in the V.sub.CC supply voltage.